Hardware Accelerator for Post-Quantum Cryptography

Overview

Leading the development of a Verilog-based hardware accelerator for the Module-Lattice-Based Digital Signature Algorithm (ML-DSA). This project enhances cryptographic operations by addressing the challenges of post-quantum security.

Key Features

• Subsystem Design: Engineered critical components like a random bit generator and NTT for polynomial multiplication.
• Hardware-Software Integration: Designed a C-based driver to ensure seamless interaction between systems.
• Scalability: Optimized architecture for efficient large-scale cryptographic applications.

Tools Used

• Hardware Languages: Verilog
• Software Tools: ModelSim, C, Python